| PART |
Description |
Maker |
| SAI01 SAI01-V1 SAI06 |
Surface-Mount, Separate Excitation Switching Type
Surface-Mount Separate Excitation Switching Type
Two-output LNB Supply And Control-voltage Regulator
Surface-Mount/ Separate Excitation Switching Type
Surface-mount and Separate Excitation Type
|
SANKEN[Sanken electric]
ALLEGRO
Sanken Electric Co.,Ltd.
|
| M5-128/120-5YI M5-128/120-5YC M5-128/160-5YI M5-19 |
Fifth Generation MACH Architecture 第五代马赫架
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 12 ns, PBGA256
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 15 ns, PBGA352
|
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
Air Cost Control
|
| SI-8050S SI-8150S SI-8000S SI-8090S SI-8120S SI-80 |
3 A SWITCHING REGULATOR, 60 kHz SWITCHING FREQ-MAX, PSFM5
Full-Mold Separate Excitation Switching Type
Full-Mold, Separate Excitation Switching Type
Full-Mold/ Separate Excitation Switching Type
|
SANKEN[Sanken electric]
|
| STA802M STA801 STA801M SANKENELECTRICCOLTD-STA801M |
2-Output Separate Excitation Step-down Switching Mode
2-OUTPUT SEPARATE EXCITATION SWITCHING TYPE
|
SANKEN[Sanken electric]
Sanken Electric Co.,Ltd.
|
| CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350 |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
|
| MC74HC367A MC74HC367AD MC74HC367ADT MC74HC367AN ON |
Telecomm/Datacomm HC/UH SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDSO16
From old datasheet system
Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
Hex 3-State NonInverting Buffer with Separate 2-Bit and 4-Bit Section High-Performance Silicon-Gate CMOS
|
Motorola Mobility Holdings, Inc.
ONSEMI[ON Semiconductor]
|
| CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV |
Memory : Sync SRAMs
18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
|
Cypress Semiconductor
|
| MAX6453 MAX6453UT16S MAX6453UT23S MAX6453UT26S MAX |
µP Supervisors with Separate VCC Reset and Manual Reset Outputs
µP Supervisors with Separate V
uP Supervisors with Separate VCC Reset and Manual Reset Outputs
?P Supervisors with Separate VCC Reset and Manual Reset Outputs
|
MAXIM INTEGRATED PRODUCTS INC
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Maxim Integrated Products, Inc.
|
| STK740-411 STK740-420 STK740-441 STK740-450 STK740 |
3.3V/5A Single Output Separate Excitation Chopper Regulator(3.3V/5A????虹?绔?????娉㈣??村?)
3.3V/5A Single Output Separate Excitation Chopper Regulator(3.3V/5A单输出独立激发斩波调整器)
3.3V/5A Single Output Separate Excitation Chopper Regulator 3.3V/5A单输出独立的励磁调节斩波
|
Sanyo Electric Co.,Ltd.
SANYO[Sanyo Semicon Device]
Sanyo Electric Co., Ltd.
|
| CY7C1418AV18-267BZC |
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1568KV18-550BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1518KV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
